1. Field of the Invention
This invention generally relates to transistor logic circuit design and, more particularly, to a high bandwidth emitter-coupled logic (ECL) design that uses a lower potential between power supplies to improve the overall power efficiency of the circuit.
2. Description of the Related Art
FIG. 1 is a schematic block diagram depicting a conventional ECL circuit, including a current-mode logic (CML) circuit and an interfacing emitter-follower circuit (prior art). There are a variety of conventional CML circuits to implement logic functions such as non-inverting buffers, inverting buffers, AND gates, NAND gates, flip-flops, latches, OR gates, exclusive-OR (XOR), and multiplexers (MUXs), to name but a few. In addition, CML functions can be combined. For example the AND and OR logic functions can be combined in a CML circuit. The emitter-follower circuit shifts the dc levels of the output signals created by the CML and generates a lower output impedance capable of driving larger loads. Vcc, and a lower voltage supply, Vee, are used in powering both the CML and the emitter follower circuits.
FIG. 2 is a detailed schematic diagram of the CML and emitter-follower circuits of FIG. 1 (prior art). Specifically, a CML (non-inverting) buffer is shown. The above-mentioned circuits are: practical in that they operate using only two power supplies, Vcc and Vee. The ability of the circuitry to operate with only two power supplies may be critical in some applications where a limited number of supplies are available. For example, a circuit embedded in a conventional integrated circuit (IC) may only have two power supplies available. However, this conventional circuitry is not necessarily power efficient. In very high-speed IC applications with gigabit data rates, the cumulative effect of inefficient circuits can result in a high thermal dissipation that requires a cooling means, such as a fan and/or a heatsink. Likewise, in battery-operated applications, the cumulative effective of inefficient circuits can result is shorter operating periods between battery charges.
It would be advantageous if a more power efficient CML circuit existed.
It would be advantageous if a more efficient emitter-follower circuit existed, for interfacing with a CML circuit.
It would be advantageous if the above-mentioned lower power CML and lower power emitter-follower circuits were interface compatible for use in an efficient ECL circuit.
The present invention describes ECL circuitry that can be operated at the highest possible bandwidth, with improved power efficiency. The present invention was designed with the realization that many systems into which ECL circuitry is embedded, now offer a plurality of available power supplies. Many of these power supply voltages are at relatively low voltage potentials. The present invention ECL circuitry makes use of these lower voltage power supplies to reduce overall power consumption.
Accordingly, a high bandwidth emitter-coupled logic (ECL) circuit is provided having reduced power consumption. The ECL circuit comprises an emitter-follower circuit with a first transistor having a collector connected to a first power supply (Vcc) and an emitter operatively connected to a second power supply (Vee2), approximately 1.5 volts less than the first power supply, through a current source. Likewise, a second transistor has a collector connected to the first power supply and an emitter operatively connected to the second power supply through a current source. The transistors receive differential input signals from an interfacing CML transistor pair. In some aspects, the first power supply is 3.3 volts and the second power supply is 1.8 volts. However, the invention is not limited to any particular set of voltages.
The ECL circuit further comprises a CML circuit having an input to receive an input signal, and is designed to implement a logic function with a level of series gated logic. Most of the fundamental logic functions can be performed using between one and four levels of series gated logic, although higher levels of series gated logic are also used. The CML circuit creates first and second differential output signals that are connected to the bases of the first and second transistors and responsive to the input signal and logic function. The CML circuit is powered by the first power supply and a third power supply (Vee3) that is approximately equal to:
Vccxe2x88x92(0.4+(the level of series gated logic)(0.9 volts)).
The CML circuit logic function can be a non-inverting buffer, inverting buffer, AND gate, NAND gate, flip-flop, latch, OR gate, exclusive-OR (XOR), multiplexer (MUX), and combinations of the above-mentioned logic functions. As a non-inverting buffer, the CML circuit includes a transistor having a collector operatively connected to the first power supply and the base of the first transistor, a base accepting an input signal, and an emitter. An emitter-coupled transistor has a collector operatively connected to the first power supply and the base of the second transistor, and a base accepting a differential signal approximately 180 degrees out of phase from the input signal. A bias transistor and a series resistor typically connect the coupled emitters to the third power supply.
Additional details of the above-mentioned ECL circuit and a low power method for creating ECL signals are provided below.